Deliverables per WorkPackage

Only Public Summary in case of a confidential deliverable

  • WP1: Project Management

    D1.1: Kick-Off Meeting

    D1.2: 18M Technical Report

    D1.3: 30M Technical Report

    D1.4: 36M Technical Report


  • WP2: Emerging Technologies

    D2.1: Definition of MRAM Building Blocks

    D2.2: Definition of OxRAM Building

    D2.3: Report on OxRAM Integration

    D2.4: Definition of TFT Building Blocks

    D2.5: BEoL FeFET NVM Block definition

    D2.6: SNN/DNN vs Tech Spec. Table

    D2.7: SNN/DNN vs updated Tech.Spec. Table


  • WP3: Integration

    D3.1: 3D µbump roadmap definition

    D3.2: 3D RC optimization

    D3.3: Comparative study wafer-to-wafer vs die- to-wafer

    D3.4: Data generation on OxRAM for Compact model generation

    D3.5: Data generation on PCRAM for Compact model generation

    D3.6: Compact model generation for OxRAM

    D3.7: Compact model generation for PCM (Analog behaviour)

    D3.8: 3D PnR flow enablement

    D3.9: Compact model generation for BEoL FeFET

    D3.10: TFT device optimization runs

    D3.11: Base wafer finishing with Ferroelectric Memory

    D3.12: Base wafer finishing with OxRAM

    D3.13: TFT standard cell study


  • WP4: Design and Architecture

    D4.1: Flexible precision blocks for DNN

    D4.2: Mixed-signal processing blocks for DNN

    D4.3: 3D DNN Module PnR

    D4.4: DNN Arch Design Scope

    D4.5: Neuron and interface circuit designs for SNN

    D4.6: TCAM Block Design for SNN

    D4.7: Routing Components for SNN

    D4.8: SNN Arch Design Scope

    D4.9: SNN module Final Design

    D4.10: DNN 3D Module PPA

    D4.11: DNN PPA: From Module to Task

    D4.12: DNN with NVM: Power management concept


  • WP5: Technology Alignment and Road- mapping

    D5.1: Report on "Designed Base wafer" Specification

    D5.2: Report on Base wafer Delivery

    D5.3: Current Infrastructure Capabilities

    D5.4: Wafer Exchange Feasibility Study

    D5.5: Projected Infrastructure Needs

    D5.6: European Neuromorphic Hardware Roadmap


  • WP6: Application Specification and Demonstration

    D6.1: Application Spec Table

    D6.2: Dataset Preparation

    D6.3: Offline software bringup (training, validation)

    D6.4: Topology and Precision Freeze

    D6.5: Chip dicing: packaging, and board bringup: MRAM

    D6.6: Chip dicing: packaging and board bringup: Ferro

    D6.7: FPGA demonstrator based on OxRAM devices

    D6.8: Dev Board Software Development

    D6.9: Application Mapping

    D6.10: Demo Benchmarking

    D6.11: Reference platform selection

    D6.12: cancelled

    D6.13: Software Freeze ,Mapping and reference 

    D6.14: Application specification and offline bring-up for ‘Human movement data analysis’

    D6.15: Reference implementation for ‘Human movement data analysis’.


  • WP7: Dissemination and exploitation

    D7.1: Dissemination Plan Sheet

    D7.2: Dissemination Plan Sheet Update

    D7.3: Final Dissemination Fact Sheet

    D7.4: Exploitation Plan Sheet

    D7.5: Exploitation Plan Sheet Update

    D7.6: Final Exploitation Fact Sheet

    D7.7: Press Release

    D7.8: Website launch